1. Field of the Invention
The present invention relates to an apparatus and a method for polishing, and particularly to an apparatus and a method for uniformly polishing a wafer to planarize a surface of the wafer having interconnection layers and an insulating film covering the interconnection layers.
2. Description of the Related Art
An apparatus for polishing according to the related art will be described with reference to FIG. 1(a) and FIG. 1(b), in accordance with the document of J. Electrochem. Soc., Vol.138, No.11, November 1991 by F. B. Kaufman et al.
In FIG. 1(a) and FIG. 1(b), reference numeral 1 indicates a polisher having a disk-like supporting board 2 which is capable of turning on a shaft 1a, and a polishing cloth 3 stuck on the supporting board 2. Reference numeral 4 indicates a disk-like wafer holder for holding and fixing on a wafer holding surface a wafer 6 having an interconnection layer and an insulating film covering the interconnection layer. A wafer holding surface is on the side opposed to the polishing cloth 3. The diameter of the wafer holder 4 is smaller than that of the polisher 1. The wafer holder 4 is turned on a shaft 4a in the same direction as the turning direction of the polisher 1. Reference numeral 5 indicates a nozzle for supplying a polishing slurry 13 containing colloidal silica.
Next, a method for polishing using the above apparatus for polishing will be described with reference to FIG. 2(A) to FIG. 2(c).
FIG. 2(a) is a sectional view of a wafer showing the state after an interlayer insulating film covering the interconnection layer is formed and before the interlayer insulating film is polished. In this figure, reference numeral 7 indicates a semiconductor substrate; 8 is a backing insulating film; 9 is a lower interconnection layer formed on the backing insulating film 8; 10a and 10b are cylindrical conductive layers for connecting the lower interconnection layer 9 to upper interconnection layers formed later, which are formed at two points on the lower interconnection layer 9; and 11 is an interlayer insulating film covering the lower interconnection layer 9 and the conductive layers 10a and 10b.
In such a state, first, the wafer 6 is held and fixed on the wafer holder 4 as shown in FIG. 1(a). Subsequently, the surface of the wafer 6 is in parallel to the surface of the polishing cloth 3. Then, the wafer holder 4 and the polisher 1 are turned in the same direction, and the wafer holder 4 is moved downward to bring the wafer 6 in contact with the polishing cloth 3. At the same time, a polishing slurry is dropped on the polishing cloth 3 through a nozzle 5.
While the wafer 6 is suitably moved on the polishing cloth 3 in such a state as to be pressed on the polishing cloth 3, the interlayer insulating film 11 on the wafer 6 is polished until the conductive layers 10a and 10b are exposed. After an elapse of a specified time, as shown in FIG. 2(b), the polishing of the interlayer insulating film 11 is completed and the surface of the wafer 6 is planarized, and concurrently the conductive layers 10a and 10b are exposed.
After that, as shown in FIG. 2(c), the upper interconnection layers 12a and 12b are formed in such a manner as to be respectively connected to the exposed conductive layers 10a and 10b, and thereby the lower interconnection layer 9 is connected to the upper interconnection layers 12a and 12b.
According to the above method for polishing of the related art, however, it is difficult to continue applying a uniform pressure over a whole surface of the wafer 6 through the wafer holder 4 while polishing. Such an unbalanced pressure results in an uneven thickness of the residual interlayer insulating film 11 through an unevenness of polishing volume over an entire surface of the wafer 6.
Thus, as shown in FIG. 3, there might arise a part where a thickness of the remaining interlayer insulating film 11 becomes thinner. As a result, when forming an upper interconnection layer there is a risk that a dielectric strength lowers between the upper interconnection layer and the lower interconnection layer, or in the worst case, the upper interconnection layer and the lower interconnection layer short-circuit.
In order to avoid such a risk, the polishing surface of the wafer 6 can be observed midway through polishing. This results, however, in a declination of throughput through some added processes including the observation by a microscope and the cleaning process of the wafer 6.